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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
DESCRIPTION
The L8C201, L8C202, L8C203, and L8C204 are dual-port First-In/FirstOut (FIFO) memories. The FIFO memory products are organized as: L8C201 -- 512 x 9-bit L8C202 -- 1024 x 9-bit L8C203 -- 2048 x 9-bit L8C204 -- 4096 x 9-bit Each device utilizes a special algorithm that loads and empties data on a firstin/first-out basis. Full and Empty flags are provided to prevent data overflow and underflow. Three additional pins are also provided to allow for unlimited expansion in both word size and depth. Depth Expansion does not result in a flow-through penalty. Multiple devices are connected with the data and control signals in parallel. The active device is determined by the Expansion In (XI) and Expansion Out (XO) signals which are daisy chained from device to device. The read and write operations are internally sequential through the use of ring pointers. No address information is required to load and unload data. The write operation occurs when the Write (W) signal is LOW. Read occurs when Read (R) goes LOW. The nine data outputs go to the high impedance state when R is HIGH. Retransmit (RT) capability allows for reset of the read pointer when RT is pulsed LOW, allowing for retransmission of data from the beginning. Read Enable (R) and Write Enable (W) must both be HIGH during a retransmit cycle, and then R is used to access the data. A Half-Full (HF) output flag is available in the single device and width expansion modes. In the depth expansion configuration, this pin provides the Expansion Out (XO) information which is used to tell the next FIFO that it will be activated. These FIFOs are designed to have the fastest data access possible. Even in lower cycle time applications, faster access time can eliminate timing bottlenecks as well as leave enough margin to allow the use of the devices without external bus drivers.
READ POINTER
FEATURES
u First-In/First-Out (FIFO) using Dual-Port Memory u Advanced CMOS Technology u High Speed -- to 10 ns Access Time u Asynchronous and Simultaneous Read and Write u Fully Expandable by both Word Depth and/or Bit Width u u u u Empty and Full Warning Flags Half-Full Flag Capability Auto Retransmit Capability Package Styles Available: * 28-pin Plastic DIP * 32-pin Plastic LCC * 28-pin Ceramic Flatpack
L8C201/202/203/204 BLOCK DIAGRAM
DATA INPUTS D8-0 9
W
WRITE CONTROL RAM ARRAY 512 x 9-bit 1K x 9-bit 2K x 9-bit 4K x 9-bit
WRITE POINTER
The FIFOs are designed for those applications requiring asychronous and simultaneous read/writes in multiprocessing and rate buffer applications.
THREE-STATE BUFFERS
R
READ CONTROL
DATA OUTPUTS Q8-0 RS FL/RT
RESET LOGIC FLAG LOGIC
EF FF
XI
EXPANSION LOGIC
XO/HF
FIFO Products
1
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
"final" read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operating has been accomplished, the Empty Flag (EF) will go HIGH after tWHEH and a valid read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO. FL/RT -- First Load/Retransmit Outputs FF -- Full Flag The Full Flag (FF) will go LOW, inhibiting further write operations, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go LOW after 512 writes for the L8C201, 1024 writes for the L8C202, 2048 writes for the L8C203, and 4096 writes for the L8C204. EF -- Empty Flag
SIGNAL DEFINITIONS Inputs RS -- Reset Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown (i.e., tWHSH before the rising edge of RS) and should not change until tSHWL after the rising edge of RS. Hall-Full Flag (HF) will be reset to high after Reset (RS). W -- Write Enable A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data setup and hold time must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRHFH, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. R -- Read Enable
This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). The FIFOs can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than the full memory has been written between resets. Retransmit will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. The retransmit feature is not compatible with the Depth Expansion Mode. XI -- Expansion In This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. D8-0 -- Data Input Data input signals for 9-bit wide data. Data has setup and hold time requirements with respect to the rising edge of W.
BS
O
2
A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/FirstOut basis, independent of any ongoing write operation. After Read Enable (R) goes HIGH, the Data Outputs (D8-0) will return to a high impedance condition until the next read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the
O
LE
TE
Q8-0 -- Data Output
The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. XO/HF -- Expansion Out/Half-Full Flag This is a dual-purpose output. In the Single Device Mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is then deasserted by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the daisy chain by providing a pulse to the next device when the previous device reaches the last location of memory.
Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read Enable (R) is in a HIGH state or the device is empty.
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e., all must be set to generate the correct composite FF or EF). 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. Bidirectional Mode
OPERATING MODES Single Device Mode A single FIFO may be used when the application requirements are for the number of words in a single device. The FIFOs are in a Single Device Configuration when the Expansion In (XI) control input is grounded. In this mode the Half-Full Flag (HF), which is an active-low output, is the active function of the combination pin XO/ HF.
1. The first device must be designated by grounding the First Load (FL) control input.
O
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device with the last device connecting back to the first.
BS
FIFO Products
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The FIFOs can easily be adapted to applications where the requirements are for greater than the number of words in a single device. Any depth can be attained by adding additional FIFOs. The FIFOs operates in the Depth Expansion configuration when the following conditions are met:
O
Depth Expansion (Daisy Chain) Mode
LE
Applications which require data buffering between two systems (each system capable of read and write Width Expansion Mode operations) can be achieved by pairing Word width may be increased simply FIFOs. Care must be taken to assure by connecting the corresponding input that the appropriate flag is monitored control signals of multiple devices. by each system (i.e., FF is monitored Status flags (EF, FF, and HF) can be on the device when W is used; EF is detected from any one device. Any monitored on the device when R is word width can be attained by adding used). Both Depth Expansion and additional FIFOs. Flag detection is Width Expansion may be used in this accomplished by monitoring the FF, mode. EF, and HF signals on either (any) device used in the width expansion configuration. Do not connect any output signals together.
TE
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2)
Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ -0.5 V to +7.0 V Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5)
Symbol VOH VOL VIH
Parameter Output High Voltage Output Low Voltage Input High Voltage
Test Condition
LE
40 90 30 95 25 100 20 110
4
TE
Min 2.4 Typ 2.0 -0.5 L8C201/202/203/20415 120 12 150
Mode Active Operation, Commercial Active Operation, Industrial Active Operation, Military
Temperature Range (Ambient) 0C to +70C -40C to +85C -55C to +125C
Supply Voltage 4.5 V VCC 5.5 V 4.5 V VCC 5.5 V 4.5 V VCC 5.5 V
L8C201/202/203/204 Max Unit V 0.4 VCC +0.3 0.8 V V
VCC = 4.5 V, IOH = -2.0 mA VCC = 4.5 V, IOL = 8.0 mA
VIL IIX IOZ ICC2 ICC3 CIN COUT
Input Low Voltage Input Leakage Current Output Leakage Current
O
(Note 3)
V A A mA mA pF pF
Ground VIN VCC
1 10
15 5 5 7
VCC Current, TTL Inactive
VCC Current, CMOS Standby Input Capacitance
Output Capacitance
O
Symbol ICC1 Parameter
BS
R VIH, GND VOUT VCC
All Inputs = VIH MIN (Note 6) All Inputs = VCC (Note 12) Ambient Temp = 25C, VCC = 4.5 V
Test Frequency = 1 MHz (Note 9)
Test Condition
(Note 5)
10 180
Unit mA
VCC Current, Active
FIFO Products
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range ASYNCHRONOUS AND RESET TIMING (ns)
L8C201/202/203/204-
25 Symbol tRLRL tRLQV tRHRL tRLRH tRHQV tRHQZ tWLWL tWLWH tWHWL tDVWH tWHDX tSLSH tSLWL tWHSH tRHSH tSHWL tSLEL tSLHH tSLFH Parameter Read Cycle Time (MHz) Read Low to Output Valid (Access Time) Read High to Read Low (Notes 8, 9) Read Low to End of Read Cycle (Notes 8, 9) Read High to Output Valid Read High to Output High Z (Note 14) Write Cycle Time (Note 9) Write Low to Write High (Notes 8, 9) Write High to End of Write Cycle (Notes 8, 9) Data Valid to Write High (Notes 8, 9) Write High to Data Change (Notes 8, 9) Reset Cycle Time (Notes 9, 10) Reset Low to Write Low (Notes 9, 10) Write High to Reset High (Notes 9, 10) Read High to Reset High (Notes 9, 10) Reset High to Write Low (Notes 9, 10) Reset Low to Empty Flag Low Reset Low to Half-Full Flag High Reset Low to Full Flag High 10 25 5 20 Min 35 25 10 15 5 15 Max 15 Min 25 15 8 12 5 15 Max Min 20 12 5 10 5 15 15 10 5 8 0 10 15 10 10 5 12 12 12 10 10 10 12 Max 10 Min 15 10 Max
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35 25 25 10 25 25 25
tRLRL tRHRL tRLRH tRLQV tRHQZ
DATA-OUT VALID
ASYNCHRONOUS READ
R
AND
WRITE OPERATION
tRLQV
BS
Q8-0
W
D8-0
O
tRHQV
DATA-OUT VALID
tWLWL
tWLWH
tWHWL tWHDX
DATA-IN VALID
tDVWH
DATA-IN VALID
RESET TIMING
O
tSLWL tSLSH tWHSH tSHWL
RS
W
tRHSH
R
tSLEL
EF
tSLHH, tSLFH
HF, FF
5
TE
35 25 10 15 0 25 15 10 10 0 20 12 8 8 0 25 15 25 15 15 10 15 15 15 12 20 12 12 8
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range FULL/EMPTY FLAG AND RETRANSMIT TIMING (ns)
L8C201/202/203/204-
25 Symbol tRLQV tRLEL tRHFH tWHEH tWLFL tTLAL tTLTH tAHTH tTHAL Parameter Read Low to Output Valid (Access Time) Read Low to Empty Flag Low Read High to Full Flag High Write High to Empty Flag High Write Low to Full Flag Low Retransmit Cycle Time Retransmit Low to End of Retransmit Cycle (Notes 8, 9, 10) Read/Write High to Retransmit High (Notes 8, 9, 10) Retransmit High to Read/Write Low (Note 9) 35 Min Max 25 25 25 25 25 25 15 Min Max 15 15 15 15 15 20 Min 12 Max 12 12 12 12 12 15 10 10 5 10 Min Max 10 10 10 10 10
FULL FLAG FROM LAST WRITE TO FIRST READ
LAST WRITE
R
W tWLFL FF
EMPTY FLAG FROM LAST READ TO FIRST WRITE
LAST READ W IGNORED READ
O
tWHEH
tTLTH tAHTH
6
LE
tRHFH
FIRST WRITE ADDITIONAL WRITES
tTLAL
IGNORED WRITE
FIRST READ
ADDITIONAL READS
R
EF DATA OUT
BS
tRLEL tRLQV
VALID
O
RETRANSMIT
RT
W, R
HF, EF, FF
TE
25 25 10 15 15 10 12 12 8 ADDITIONAL WRITES
FIRST READ
VALID
tTHAL
FLAG VALID
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range FULL/HALF-FULL/EMPTY FLAG TIMING (ns)
L8C201/202/203/204-
25 Symbol tRHFH tEHRH tRHHH tWHEH tWLHL tFHWH Parameter Read High to Full Flag High Read Pulse Width After Empty Flag High Read High to Half-Full Flag High Write High to Empty Flag High Write Low to Half-Full Flag Low Write Pulse Width After Full Flag High (Note 9) 25 25 25 25 25 15 Min Max 25 15 15 15 15 12 15 Min Max 15 12 12 12 12 10 Min 12 Max 12 10 10 10 10 10 Min Max 10
EMPTY FLAG TIMING
W
tWHEH
EF
LE O
tRHFH
MORE THAN HALF-FULL tWLHL
7
R
FULL FLAG TIMING
W
FF
R
HALF-FULL FLAG TIMING
BS
HALF-FULL OR LESS
O
W
R
HF
TE
tEHRH
tFHWH
HALF-FULL OR LESS
tRHHH
FIFO Products
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range EXPANSION TIMING (ns)
L8C201/202/203/204-
25 Symbol tALOL tAHOH tXLXH tXHXL tALXL Parameter Read/Write to Expansion Out Low (Note 11) Read/Write to Expansion Out High (Note 11) Expansion In Pulse Width (Notes 9, 11) Expansion In High to Expansion In Low (Notes 9, 11) Read/Write Low to Expansion In Low (Notes 9, 11) 25 10 15 Min Max 25 25 15 10 12 15 Min Max 15 15 12 10 8 Min 12 Max 12 12 10 10 8 10 Min Max 12 12
EXPANSION OUT
WRITE TO LAST PHYSICAL LOCATION
W
R
tALOL
XO
tAHOH
LE
tALOL
tXHXL tALXL READ FROM FIRST PHYSICAL LOCATION
8
EXPANSION IN
tXLXH
XI
tALXL
W
WRITE TO FIRST PHYSICAL LOCATION
R
O
BS
O
TE
READ FROM LAST PHYSICAL LOCATION tAHOH
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range ASYNCHRONOUS AND RESET TIMING (ns)
L8C201/202/203/204-
40 Symbol tRLRL tRLQV tRHRL tRLRH tRHQV tRHQZ tWLWL tWLWH tWHWL tDVWH tWHDX tSLSH tSLWL tWHSH tRHSH tSHWL tSLEL tSLHH tSLFH Parameter Read Cycle Time (MHz) Read Low to Output Valid (Access Time) Read High to Read Low (Notes 8, 9) Read Low to End of Read Cycle (Notes 8, 9) Read High to Output Valid Read High to Output High Z (Note 14) Write Cycle Time (Note 9) Write Low to Write High (Notes 8, 9) Write High to End of Write Cycle (Notes 8, 9) Data Valid to Write High (Notes 8, 9) Write High to Data Change (Notes 8, 9) Reset Cycle Time (Notes 9, 10) Reset Low to Write Low (Notes 9, 10) Write High to Reset High (Notes 9, 10) Read High to Reset High (Notes 9, 10) Reset High to Write Low (Notes 9, 10) Reset Low to Empty Flag Low Reset Low to Half-Full Flag High Reset Low to Full Flag High 10 40 5 25 Min 50 40 10 30 5 20 Max Min 40 30 10 20 5 15 30 20 10 12 0 20 30 20 20 10 40 40 40 30 30 30 30 Max 20 Min 30 20 Max
LE
tRLRL tRHRL tRLRH tRLQV tRHQZ
DATA-OUT VALID
ASYNCHRONOUS READ
R
AND
WRITE OPERATION
tRLQV
BS
Q8-0
W
D8-0
O
tRHQV
DATA-OUT VALID
tWLWL
tWLWH
tWHWL tWHDX
DATA-IN VALID
tDVWH
DATA-IN VALID
RESET TIMING
O
tSLWL tSLSH tWHSH tSHWL
RS
W
tRHSH
R
tSLEL
EF
tSLHH, tSLFH
HF, FF
9
TE
50 40 10 20 0 40 30 10 18 0 40 50 40 40 10 50 50 50 30 40 30 30 10
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range FULL/EMPTY FLAG AND RETRANSMIT TIMING (ns)
L8C201/202/203/204-
40 Symbol tRLQV tRLEL tRHFH tWHEH tWLFL tTLAL tTLTH tAHTH tTHAL Parameter Read Low to Output Valid (Access Time) Read Low to Empty Flag Low Read High to Full Flag High Write High to Empty Flag High Write Low to Full Flag Low Retransmit Cycle Time Retransmit Low to End of Retransmit Cycle (Notes 8, 9, 10) Read/Write High to Retransmit High (Notes 8, 9, 10) Retransmit High to Read/Write Low (Note 9) 50 40 40 10 Min Max 40 30 35 35 35 40 30 30 10 Min 30 Max 30 30 30 30 30 30 20 20 10 20 Min Max 20 20 20 20 20
FULL FLAG FROM LAST WRITE TO FIRST READ
LAST WRITE
R
W tWLFL FF
EMPTY FLAG FROM LAST READ TO FIRST WRITE
LAST READ W IGNORED READ
O
tWHEH
tTLTH tAHTH
10
LE
tRHFH
FIRST WRITE ADDITIONAL WRITES
tTLAL
IGNORED WRITE
FIRST READ
ADDITIONAL READS
R
EF DATA OUT
BS
tRLEL tRLQV
VALID
O
RETRANSMIT
RT
W, R
HF, EF, FF
TE
ADDITIONAL WRITES
FIRST READ
VALID
tTHAL
FLAG VALID
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range FULL/HALF-FULL/EMPTY FLAG TIMING (ns)
L8C201/202/203/204-
40 Symbol tRHFH tEHRH tRHHH tWHEH tWLHL tFHWH Parameter Read High to Full Flag High Read Pulse Width After Empty Flag High Read High to Half-Full Flag High Write High to Empty Flag High Write Low to Half-Full Flag Low Write Pulse Width After Full Flag High (Note 9) 40 40 50 35 50 30 Min Max 35 30 40 30 40 20 Min 30 Max 30 20 30 20 30 20 Min Max 20
EMPTY FLAG TIMING
W
tWHEH
EF
LE O
tRHFH
MORE THAN HALF-FULL tWLHL
11
R
FULL FLAG TIMING
W
FF
R
HALF-FULL FLAG TIMING
BS
HALF-FULL OR LESS
O
W
R
HF
TE
tEHRH
tFHWH
HALF-FULL OR LESS
tRHHH
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range EXPANSION TIMING (ns)
L8C201/202/203/204-
40 Symbol tALOL tAHOH tXLXH tXHXL tALXL Parameter Read/Write to Expansion Out Low (Note 11) Read/Write to Expansion Out High (Note 11) Expansion In Pulse Width (Notes 9, 11) Expansion In High to Expansion In Low (Notes 9, 11) Read/Write Low to Expansion In Low (Notes 9, 11) 40 10 10 Min Max 40 40 30 10 10 Min 30 Max 30 30 20 10 10 20 Min Max 20 20
EXPANSION OUT
WRITE TO LAST PHYSICAL LOCATION
W
R
tALOL
XO
tAHOH
LE
tALOL
tXHXL tALXL READ FROM FIRST PHYSICAL LOCATION
12
EXPANSION IN
tXLXH
XI
tALXL
W
WRITE TO FIRST PHYSICAL LOCATION
R
O
BS
O
TE
READ FROM LAST PHYSICAL LOCATION tAHOH
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
FIGURE 1. FIFO MEMORY (DEPTH EXPANSION) BLOCK DIAGRAM
W
FF
XO EF 9 9
R Q8-0 VCC
D8-0
L8C20X
XI FL
XO 9
L8C20X
XI FL
9
XO FF 9 EF 9
L8C20X
XI FL
RS
TABLE 1.
MODE Reset
RESET AND RETRANSMIT (SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE)
INPUTS RS 0 RT X 0 INTERNAL STATUS Write Pointer Location Zero Unchanged Increment EF 0 X X OUTPUTS FF 1 X X HF 1 X X XI 0 Read Pointer
Retransmit
Read/Write
BS
1 0 1 1 0 INPUTS RT 0 1 (2) RS 0 0 1 XI
TABLE 2.
RESET AND FIRST LOAD TRUTH TABLE (DEPTH EXPANSION/COMPOUND EXPANSION MODE)
INTERNAL STATUS Write Pointer Location Zero Location Zero Disabled X OUTPUTS EF 0 0 X FF 1 1 X Read Pointer
O
MODE
Reset First Device Reset All Others Read/Write
(1) (1) (1)
(1) See Figure 1 (Depth Expansion Block Diagram) (2) Unchanged
O
Location Zero Location Zero Increment Location Zero X
13
Location Zero Disabled
LE
FIFO Products
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TE
FULL
FF
EF
EMPTY
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
NOTES
1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability of the tested device. 2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This product provides hard clamping of transient undershoot. Input levels below ground will be clamped beginning at -0.6 V. A current in excess of 100 mA is required to reach -2 V. The device can withstand indefinite operation with inputs as low as -3 V subject only to power dissipation and bond wire fusing constraints. 4. "Typical" supply current values are not shown but may be approximated. At a VCC of +5.0 V, an ambient temperature of +25C and with nominal manufacturing parameters, the operating supply currents will be approximately 3/4 or less of the maximum values shown. 5. Tested with outputs open and data inputs changing at the specified read and write cycle rate. The device is neither full or empty for the test. 6. Tested with outputs open in the worst static input control signal combination (i.e., W, R, XI, FL, and RS). 7. These parameters are guaranteed but not 100% tested. ments of all parts. Responses from the internal circuitry are specified from the point of view of the device. Access time, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 10. When cascading devices, the reset pulse width must be increased to equal tSLSH + tSLHH. 11. It is not recommended that Logic Devices and other vendor parts be cascaded together. The parts are designed to be pinfor-pin compatible but temperature and voltage compensation may vary from vendor to vendor. Logic Devices can only guarantee the cascading of Logic Devices parts to other Logic Devices parts. 12. Tested with output open and RS = FL = XI = R = W = VCC.
FIGURE 2a.
R1 480
+5 V
OUTPUT
INCLUDING JIG AND SCOPE
30 pF
R2 255
TE
+5 V
OUTPUT INCLUDING JIG AND SCOPE
FIGURE 2b.
R1 480
14. Transition is measured 200 mV from steady state voltage with specified loading in Fig. 2b. This parameter is sampled and not 100% tested. 15. This product is a very high speed device and care must be taken during testing in order to realize valid test information. Inadequate attention to setups and procedures can cause a good part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper terminations must be used.
LE
14
13. At any given temperature and voltage condition, output disable time is less than output enable time for any given device.
5 pF
R2 255
FIGURE 3.
+3.0 V 10% 90% 90% 10% <3 ns
GND
<3 ns
8. Test conditions assume input transition times of 5 ns or less, reference levels of 1.5 V, output loading for specified IOL and IOH plus 30 pF (Fig. 2a), and input pulse levels of 0 to 3.0 V (Fig. 3).
O
9. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. For example, tRLRH is specified as a minimum since the external system must supply at least that much time to meet the worst-case require-
BS
O
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C201 -- ORDERING INFORMATION
28-pin -- 0.3" wide 28-pin -- 0.6" wide
Speed
Plastic DIP (P10)
LE
15
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C201PC25 L8C201PC15 L8C201PC12 L8C201PC10
O
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C201PI25 L8C201PI15 L8C201PI12 L8C201PI10 L8C201NI25 L8C201NI15 L8C201NI12 L8C201NI10
O
BS
TE
Plastic DIP (P9) L8C201NC25 L8C201NC15 L8C201NC12 L8C201NC10
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C201 -- ORDERING INFORMATION
32-pin -- 0.490" x 0.590" 28-pin
D3 D8 W NC VCC D4 D5
43
11 12
23 22
13 21 14 15 16 17 18 19 20
Speed
Plastic J-Lead Chip Carrier (J6)
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C201JC25 L8C201JC15 L8C201JC12 L8C201JC10
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C201JI25 L8C201JI15 L8C201JI12 L8C201JI10
-55C to +125C -- COMMERCIAL SCREENING
O
40 ns 30 ns 20 ns
BS
O
L8C201MM40 L8C201MM30 L8C201MM20 L8C201MMB40 L8C201MMB30 L8C201MMB20
-55C to +125C -- MIL-STD-883 COMPLIANT
40 ns 30 ns 20 ns
LE
16
TE
Ceramic Flatpack (M2)
D2 D1 D0 XI FF Q0 Q1 NC Q2
5 6 7 8 9 10
2 1 32 31 30 29 28 27
Top View
26 25 24
D6 D7 NC FL/RT RS EF XO/HF Q7 Q6
Q3 Q8 GND NC R Q4 Q5
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202 -- ORDERING INFORMATION
28-pin -- 0.3" wide 28-pin -- 0.6" wide
Speed
Plastic DIP (P10)
LE
17
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C202PC25 L8C202PC15 L8C202PC12 L8C202PC10
O
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C202PI25 L8C202PI15 L8C202PI12 L8C202PI10 L8C202NI25 L8C202NI15 L8C202NI12 L8C202NI10
O
BS
TE
Plastic DIP (P9) L8C202NC25 L8C202NC15 L8C202NC12 L8C202NC10
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202 -- ORDERING INFORMATION
32-pin -- 0.490" x 0.590" 28-pin
D3 D8 W NC VCC D4 D5
43
11 12
23 22
13 21 14 15 16 17 18 19 20
Speed
Plastic J-Lead Chip Carrier (J6)
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C202JC25 L8C202JC15 L8C202JC12 L8C202JC10
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C202JI25 L8C202JI15 L8C202JI12 L8C202JI10
-55C to +125C -- COMMERCIAL SCREENING
O
40 ns 30 ns 20 ns
BS
O
L8C202MM40 L8C202MM30 L8C202MM20 L8C202MMB40 L8C202MMB30 L8C202MMB20
-55C to +125C -- MIL-STD-883 COMPLIANT
40 ns 30 ns 20 ns
LE
18
TE
Ceramic Flatpack (M2)
D2 D1 D0 XI FF Q0 Q1 NC Q2
5 6 7 8 9 10
2 1 32 31 30 29 28 27
Top View
26 25 24
D6 D7 NC FL/RT RS EF XO/HF Q7 Q6
Q3 Q8 GND NC R Q4 Q5
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C203 -- ORDERING INFORMATION
28-pin -- 0.3" wide 28-pin -- 0.6" wide
Speed
Plastic DIP (P10)
LE
19
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C203PC25 L8C203PC15 L8C203PC12 L8C203PC10
O
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C203PI25 L8C203PI15 L8C203PI12 L8C203PI10 L8C203NI25 L8C203NI15 L8C203NI12 L8C203NI10
O
BS
TE
Plastic DIP (P9) L8C203NC25 L8C203NC15 L8C203NC12 L8C203NC10
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C203 -- ORDERING INFORMATION
32-pin -- 0.490" x 0.590" 28-pin
D3 D8 W NC VCC D4 D5
43
11 12
23 22
13 21 14 15 16 17 18 19 20
Speed
Plastic J-Lead Chip Carrier (J6)
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C203JC25 L8C203JC15 L8C203JC12 L8C203JC10
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C203JI25 L8C203JI15 L8C203JI12 L8C203JI10
-55C to +125C -- COMMERCIAL SCREENING
O
40 ns 30 ns 20 ns
BS
O
L8C203MM40 L8C203MM30 L8C203MM20 L8C203MMB40 L8C203MMB30 L8C203MMB20
-55C to +125C -- MIL-STD-883 COMPLIANT
40 ns 30 ns 20 ns
LE
20
TE
Ceramic Flatpack (M2)
D2 D1 D0 XI FF Q0 Q1 NC Q2
5 6 7 8 9 10
2 1 32 31 30 29 28 27
Top View
26 25 24
D6 D7 NC FL/RT RS EF XO/HF Q7 Q6
Q3 Q8 GND NC R Q4 Q5
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C204 -- ORDERING INFORMATION
28-pin -- 0.3" wide 28-pin -- 0.6" wide
Speed
Plastic DIP (P10)
LE
21
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C204PC25 L8C204PC15 L8C204PC12 L8C204PC10
O
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C204PI25 L8C204PI15 L8C204PI12 L8C204PI10 L8C204NI25 L8C204NI15 L8C204NI12 L8C204NI10
O
BS
TE
Plastic DIP (P9) L8C204NC25 L8C204NC15 L8C204NC12 L8C204NC10
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C204 -- ORDERING INFORMATION
32-pin -- 0.490" x 0.590" 28-pin
D3 D8 W NC VCC D4 D5
43
11 12
23 22
13 21 14 15 16 17 18 19 20
Speed
Plastic J-Lead Chip Carrier (J6)
0C to +70C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C204JC25 L8C204JC15 L8C204JC12 L8C204JC10
-40C to +85C -- COMMERCIAL SCREENING
25 15 12 10 ns ns ns ns L8C204JI25 L8C204JI15 L8C204JI12 L8C204JI10
-55C to +125C -- COMMERCIAL SCREENING
O
40 ns 30 ns 20 ns
BS
O
L8C204MM40 L8C204MM30 L8C204MM20 L8C204MMB40 L8C204MMB30 L8C204MMB20
-55C to +125C -- MIL-STD-883 COMPLIANT
40 ns 30 ns 20 ns
LE
22
TE
Ceramic Flatpack (M2)
D2 D1 D0 XI FF Q0 Q1 NC Q2
5 6 7 8 9 10
2 1 32 31 30 29 28 27
Top View
26 25 24
D6 D7 NC FL/RT RS EF XO/HF Q7 Q6
Q3 Q8 GND NC R Q4 Q5
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
FIFO Products
03/04/99-LDS.8C201/2/3/4-H

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